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ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 0 ? revision history revision description issue date rev. 1.0 initial issue sep.06.2012 rev. 1.1 rev. 1.2 add 25 & 40 spec for i sb1 & i dr on page 4 & page 9 delete ll grade for ordering information on page 11 correct typo error on the column ?ub#?, ?lb#? of truth table for row ?byte read? ?byte writ e? and ?output disable? at page 4: ?x? revised to be ?l? no v .06.2012 july.08.2013
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 1 ? features ? fast access time : 55/70ns ? low power consumption: operating current : 45/30ma (typ.) standby current : 10 a (typ.) sl-version ? single 2.7v ~ 3.6v power supply ? all inputs and outputs ttl compatible ? fully static operation ? tri-state output ? data byte control : (i) byte# fixed to v cc lb# controlled dq0 ~ dq7 ub# controlled dq8 ~ dq15 (ii) byte# fixed to v ss dq15 used as address pin, while dq8~dq14 pins not used ? data retention voltage : 1.2v (min.) ? green package available ? package : 48-pin 12mm x 20mm tsop-i general description the ly62l205016a is a 33,554,432-bit low power cmos static random ac cess memory organized as 2,097,152 words by 16 bits or 4,194,304 words by 8 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the ly62l205016a is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. the ly62l205016a operates from a single power supply of 2.7v ~ 3.6v and all inputs and outputs are fully ttl compatible product family product family operating temperature vcc range speed power dissipation standby(i sb1, typ.) operating(icc,typ.) ly62l205016a 0 ~ 70 2.7 ~ 3.6v 55/70ns 10a(sl) 45/30ma ly62l205016a(i) -40 ~ 85 2.7 ~ 3.6v 55/70ns 10a(sl) 45/30ma
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 2 ? functional block diagram control circuit decoder 2048kx16/4096kx8 memory array column i/o a0~a20 /a-1~a20 vcc vss dq8-dq15 upper byte dq0-dq7 lower byte i/o data circuit ce2 we# oe# lb# ub# ce# byte# pin description symbol description a0 ? a20 address inputs(word mode) a-1 ? a20 address inputs(byte mode) dq0 ? dq15 data inputs/outputs ce#, ce2 chip enable input we# write enable input oe# output enable input lb# lower byte control ub# upper byte control byte# byte enable v cc power supply v ss ground
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 3 ? pin configuration tsop-i a15 a14 a13 a12 a8 ly62l205016a xxxxx xxxxx 8 7 6 5 4 3 2 1 a11 a10 a9 a20 a19 we# ce2 nc ub# lb# a18 a17 a7 a6 a5 a4 a3 a2 a1 14 13 12 11 10 9 16 15 22 21 20 19 18 17 24 23 dq13 byte# dq15/a-1 dq7 dq14 dq6 44 41 42 43 a16 vss 48 47 45 46 33 36 35 34 38 39 40 37 25 28 27 26 30 31 32 29 dq12 dq5 dq4 vcc dq11 dq3 dq10 dq2 dq1 dq9 dq8 dq0 oe# vss ce# a0 absolute maximun ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 4.6 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v operating temperature t a 0 to 70(c grade) -40 to 85(i grade) storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma *stresses greater than those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliabil ity.
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 4 ? truth table mode ce# ce2 byte# oe# we# lb# ub# i/o operation supply current dq0-dq7 dq8-dq14 dq15 standby h x x x l x x x h x x x x x x x x h x x h high ? z high ? z high ? z high ? z high ? z high ? z high ? z high ? z high ? z i sb ,i sb1 output disable l l l h h h h h l h h h h h h l x l x l l high ? z high ? z high ? z high ? z high ? z high ? z high ? z high ? z a-1 i cc ,i cc1 read l l l h h h h h h l l l h h h l h l h l l d out high ? z d out high ? z d out d out high ? z d out d out i cc ,i cc1 write l l l h h h h h h x x x l l l l h l h l l d in high ? z d in high ? z d in d in high ? z d in d in i cc ,i cc1 byte# read l h l l h l l dout high ? z a-1 i cc ,i cc1 byte # write l h l x l l l din high ? z a-1 i cc ,i cc1 note: h = v ih , l = v il , x = don't care. dc electrical characteristics parameter symbol test condition min. typ. * 4 max. unit supply voltage v cc 2.7 3.0 3.6 v input high voltage v ih *1 2.2 - v cc +0.3 v input low voltage v il *2 - 0.2 - 0.6 v input leakage current i li v cc R v in R v ss - 1 - 1 a output leakage current i lo v cc R v out R v ss output disabled - 1 - 1 a output high voltage v oh i oh = -1m a 2.2 2.7 - v output low voltage v ol i ol = 2m a - - 0.4 v average operating power supply current i cc cycle time = min. ce# = v il and ce2 = v ih i i/o = 0ma other pins at v il or v ih - 55 - 45 80 ma - 70 - 30 60 ma i cc1 cycle time = 1 s ce# Q 0.2v and ce2 R v cc -0.2v i i/o = 0ma other pins at 0.2v or v cc -0.2v - 10 20 ma standby power supply current i sb ce# = v ih or ce2 = v il other pins at v il or v ih - 0.3 2 ma i sb1 ce# v R cc -0.2v or ce2 Q 0.2v other pins at 0.2v or v cc -0.2v - sl - sli 25 - 10 18 a 40 - 10 18 a -sl - 10 80 a -sli - 10 120 a notes: 1. v ih (max) = v cc + 2.0v for pulse width less than 6ns. 2. v il (min) = v ss - 2.0v for pulse width less than 6ns. 3. over/undershoot specifications ar e characterized on engineering evaluati on stage, not for mass production test. 4. typical values are included for reference only and are not guaranteed or tested. typical valued are measured at v cc = v cc (typ.) and t a = 25
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 5 ? capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. ma x unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by devic e characterization, but not production tested. ac test conditions input pulse levels 0.2v to v cc -0.2v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf + 1ttl, i oh / i ol = -1ma/2m a ac electrical characteristics (1) read cycle parameter sym. ly62l205016a-55 ly62l205016a-70 unit min. max. min. max. read cycle time t rc 55 - 70 - ns a ddress access time t aa - 55 - 70 ns chip enable access time t ace - 55 - 70 ns output enable access time t oe - 30 - 35 ns chip enable to output in low-z t clz * 10 - 10 - ns output enable to output in low-z t olz * 5 - 5 - ns chip disable to output in high-z t chz * - 20 - 25 ns output disable to output in high-z t ohz * - 20 - 25 ns output hold from address change t oh 10 - 10 - ns lb#, ub# a ccess time t ba - 55 - 70 ns lb#, ub# to high-z output t bhz * - 25 - 30 ns lb#, ub# to low-z output t blz * 10 - 10 - ns (2) write cycle parameter sym. ly62l205016a-55 ly62l205016a-70 unit min. max. min. max. write cycle time t wc 55 - 70 - ns a ddress valid to end of write t aw 50 - 60 - ns chip enable to end of write t cw 50 - 60 - ns a ddress set-up time t as 0-0- ns write pulse width t wp 45 - 55 - ns write recovery time t wr 0-0- ns data to write time overlap t dw 25 - 30 - ns data hold from end of write time t dh 0-0- ns output active from end of write t ow * 5-5- ns write to output in high-z t whz * - 20 - 25 ns lb#, ub# valid to end of write t bw 45 - 60 - ns *these parameters are guaranteed by device characterization, but not production tested.
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 6 ? timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 (ce# and ce2 and oe# controlled) (1,3,4,5) dout data valid high-z high-z t clz t olz t chz t ohz t oh oe# t oe lb#,ub# t bhz t ace t ba t blz ce# t aa address t rc ce2 notes : 1.we#is high for read cycle. 2.device is continuously selected oe# = low, ce# = low, ce2 = high, lb# or ub# = low . 3.address must be valid prior to or coincident with ce# = low, ce2 = high, lb# or ub# = low transition; otherwise t aa is the limiting parameter. 4.t clz , t blz, t olz , t chz, t bhz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t bhz is less than t blz , t ohz is less than t olz.
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 7 ? write cycle 1 (we# controlled) (1,2,3,5,6) dout din data valid t dw t dh (4) high-z t whz we# t wp t cw t wr t as (4) t ow lb#,ub# t bw ce# t aw address t wc ce2 write cycle 2 (ce# and ce2 controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# lb#,ub# t cw t wp t bw ce# address t wr t as t aw t wc ce2
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 8 ? write cycle 3 (lb# ,ub# controlled) (1,2,5,6) dout din data valid t dw t dh (4) high-z t whz we# lb#,ub# t cw t as t wp t bw ce# address t wr t aw t wc ce2 notes : 1.we#,ce#, lb#, ub# must be high or ce2 must be low during all address transitions. 2.a write occurs during the overlap of a low ce#, high ce2, low we#, lb# or ub# = low. 3.during a we# controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the out put state, and input signals must not be applied. 5.if the ce#, lb#, ub# low transition and ce2 high transition o ccurs simultaneously with or after we# low transition, the outpu ts remain in a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state.
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 9 ? data retention characteristics parameter symbol test cond ition min. typ. max. unit v cc for data retention v dr ce# v R cc - 0.2v or ce2 Q 0.2v 1.2 - 3.6 v data retention current i dr v cc = 1.2v ce# v R cc -0.2v or ce2 Q 0.2v other pins at 0.2v or v cc -0.2v -sl -sli 25 - 8 16 a 40 - 8 16 a -sl - 8 80 a -sli - 8 120 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time data retention waveform low vcc data retention waveform (1) (ce# controlled) vcc ce# v dr R 1.2v ce# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.) low vcc data retention waveform (2) (ce2 controlled) vcc ce2 v dr R 1.2v ce2 Q 0.2v vcc(min.) v il t r t cdr v il vcc(min.) low vcc data retention waveform (3) (lb#, ub# controlled) vcc lb#,ub# v dr R 1.2v lb#,ub# v R cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.)
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 10 ? package outline dimension 48-pin 12mm x 20mm tsop-i package outline dimension
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 11 ? ordering information package type access time (speed)(ns) power type temperature range( ) packing type lyontek item no. 48-pin 12mm x 20mm tsop-i 55 special ultra low power 0 ~70 tray LY62L205016ALL-55SL tape reel LY62L205016ALL-55SLt -40 ~85 tray LY62L205016ALL-55SLi tape reel LY62L205016ALL-55SLit 70 special ultra low power 0 ~70 tray ly62l205016all-70sl tape reel ly62l205016all-70slt -40 ~85 tray ly62l205016all-70sli tape reel ly62l205016all-70slit
ly62l205016a rev. 1.2 32m bits ( 2mx16 / 4mx8 swit chable) low power cmos sram lyontek inc. reserves the rights to change the specificati ons and products without notice. 5f, no. 2, industry e. rd. ix, science-ba sed industrial park, hsinchu 300, taiwan. tel: 886-3-6668838 fax: 886-3-6668836 12 ? this page is left blank intentionally.

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